1. Field
The present disclosure relates generally to electronics, and more particularly, to decoupling capacitors for integrated circuits.
2. Background
In semiconductor design, standard cell methodology typically involves designing integrated circuits having various functionality using standard components and interconnect structures. These activities are typically facilitated within a computer-aided design environment. Standard cell methodology uses abstraction wherein low level integrated circuit synthesis is replaced by a more abstract, higher-level functional representation. Cell-based methodologies allow one designer to focus on the high-level aspect of design, while another designer focuses on the physical implementation.
The physical implementation of the integrated circuit or “chip,” begins with the standard cell. The standard cell is generally organized in layers with transistors being formed in the lower layers and interconnects formed above. A large number of these cells are then distributed across the chip and interconnected to provide operational functionality. Typically, the cells have a constant lateral dimension which allows them to be arranged in rows. Together, these rows form the core of the chip. The core is surrounded by a number of larger cells arranged along the periphery of the chip. The larger cells contain input/output (I/O) drivers formed with transistors having wider channel lengths, thicker oxide layers, and higher threshold voltages to interface with higher voltage off-chip devices.
The cells that make up the core are distributed on the chip using a standard automation tool. Due to various design rules imposed by the foundry, various sections within the core may lack a functioning cell. These sections are sometimes referred to as “white space.” Decoupling capacitors are often used in the white space to improve noise performance. In the past, decoupling capacitors have been implemented using MOS transistors designed for I/O drivers.
In order to meet the increasing demand for smaller and more powerful devices, the semiconductor industry continues to evolve to smaller process geometries. Today, the size of the standard cell has been reduced using 20 nm or smaller geometry technology. This technology, however, presents certain challenges when attempting to provide decoupling in the white space of the core. The MOS capacitors designed for I/O drivers no longer meet the requirements of the smaller geometries being implemented in the core. Smaller geometry MOS capacitors cannot be used as decoupling capacitors due to high leakage current and electrostatic discharge (ESD) concerns. Accordingly, there is a need in the art for smaller geometry decoupling capacitors configured to have low leakage current with reduced ESD concerns.